1. Field of the Invention
The present invention relates to a display panel and a method of manufacturing the same and, more particularly, to a panel and a manufacturing method which can to reduce the removing photoresist time and to prevent a result of photoresist residues.
2. Description of the Related Art
FIG. 1 schematically shows a display panel. The display panel includes a display area 11, a periphery area 12, and a blank area. The periphery area 12 is electrically connected to the display area 11 to control a display image shown in the display area 11. Several thin film transistors, storage capacitors, and driving devices are formed in the display area 11 and the periphery area 12, respectively. As shown in FIG. 1, the dotted lines between the periphery area 12 and the display area 11 represent metal lines formed in a substrate. The metal lines are electrically connected to the periphery area 12 and the display area 11. Furthermore, a dotted circle in FIG. 1 represents a pixel in the display area 11. Each pixel is defined by signal lines, such as scan lines and data lines, crossing over each other (not shown in FIG. 1). At least one thin film transistor (not shown in FIG. 1) and one storage capacitor (such as Cst, Clc, etc) are formed in each pixel. The portions besides the display area 11 and the periphery area 12 are defined as blank areas including 13a, 13b, and 13c, wherein the blank area 13c is the largest one among them.
In the development of display panels (such as a thin film transistor liquid crystal display panel (TFT-LCD), etc), the manufacturing processes for decreasing the number of masks and reducing the manufacturing time and cost have been revealed. However, the photoresist residues and conductive layers remained in the blank area are the issues of concern in the conventional process of manufacturing TFT-LCD, especially the residues remained in the largest blank area 13c. 
FIG. 2A˜FIG. 2H are a conventional method of manufacturing a display panel for decreasing the number of the masks. Referring to FIG. 1 and FIG. 2A˜FIG. 2H together, a first metal layer is deposited on a substrate 20. Then, the first metal layer is etched (by using a first mask) to form a gate electrode 211 and a bottom electrode 241 of a storage capacitor (Cst) within the display area 11 of the substrate 20, as shown in FIG. 2A.
Afterward, a gate insulating layer 212 is formed on the gate electrode 211. For example, the gate insulating layer 212 is made of silicon nitride (SiNx). The gate insulating layer 212 covers the bottom electrode 241 of the storage capacitor (Cst) and the blank area 13b/13c of the substrate 20. Next, a channel layer 213, an ohmic contact layer 214, and a second metal layer 215 are sequentially formed on the gate insulating layer 212. The second metal layer 215 is then etched (by using a second mask) to form a source S, a drain D, and a channel region 216 between the source S and the drain D, as shown in FIG. 2B.
Next, a passivation layer 217 is disposed to cover the source S, the drain D, and the channel region 216 in area of the TFT device. The passivation layer 217 is also formed on a portion of the gate insulating layer 212 of the bottom electrode 241 of the storage capacitor and on the gate insulating layer 212 in the blank area 13b/13c, as shown in FIG. 2C. For example, the passivation layer 217 is made of silicon nitride (SiNx). Furthermore, the gate insulating layer 212 and the passivation layer 217 can be called as an insulating multilayer hereinafter.
Afterward, photoresist layers 218a, 218b and 218c are formed on the passivation layer 217 by using a mask with a halftone area (a third mask not shown in FIG. 2D). The photoresist layer 218a is formed in a region corresponding to the TFT device. The photoresist layer 218b is formed within the display area 11 except the region corresponding to the TFT device. The photoresist layer 218c is formed in the blank area 13b/13c, as shown in FIG. 2D. Also, a hole 219 is formed in the display area 11 to expose part of the drain/source in the TFT device, as shown in FIG. 2E. The height of the photoresist layer 218a is substantially identical to that of the photoresist layer 218c. The height of the photoresist layer 218b is less than that of the photoresist layers 218a and 218c. 
Next, the photoresist layers 218a, 218b, and 218c are ashed. The photoresist layer 218b which is not in the TFT device is completely removed. The photoresist layer 218a′ over the TFT device and the photoresist layer 218c′ in the blank area 13b/13c are partially removed and become thinner as shown in FIG. 2F.
Then, a conductive layer 220 is formed to cover the photoresist layer 218a′ over the TFT device in the display area 11 and the photoresist layer 218c′ in the blank area 13b/13c. As shown in FIG. 2G, the conductive layer 220 also covers a portion of the passivation layer 217 on the storage capacitor (Cst) in the display area 11, and acts as a top electrode of the storage capacitor. The conductive layer 220 could be made of indium tin oxide (ITO).
Finally, the photoresist layers are removed by a lift-off step. As shown in FIG. 2H, the photoresist layer 218a′ in the display area 11, the conductive layer 220 on the photoresist layer 218a′ in the display area 11, the photoresist layer 218c′ in the blank area 13b/13c and the conductive layer 220 on the photoresist layer 218c′ in the blank area 13b/13c are removed together in this step.
In the above manufacturing process for decreasing the number of masks, the photoresist layers should be removed completely under an ideal lift-off condition. However, in the restricted manufacturing time, it is not easy to completely remove the photoresist layers with large area, such as in the blank area 13c. Accordingly, residues of the photoresist layers and the conductive layers could be easily remained. Thus, the quality of the display panel is decreased. In general, residues remained is due to the length L of the photoresist layer (referring to FIG. 2G, L is marked on the photoresist layer 218c′) is greater than 1500 μm.